1. Field of the Invention
The present invention relates to a quad flat flip packaging process and a leadframe therefor. More particularly, the present invention relates to a quad flat flip packaging process and a leadframe therefor directed to lowering the manufacturing cost and preventing the delamination between the molding compound material and the leads.
2. Description of the Related Art
Semiconductor Industry is one of the most developed hi-technology in recent years. With the technology advancing, the hi-tech electronics industries have developed thinner, lighter and more compact products with artificial intelligence and better functions. In the manufacturing process of semiconductor products, a leadframe is one of the most popular elements in package. A quad flat package (QFP) is divided into I-type (QFI), J-type (QFJ) and non-lead-type (QFN), according to the shape of the lead of leadframes. It is noted that a QFP has relatively shorter signal traces and a relatively higher speed for signal transferring, and thus becomes mainstream in the package field with low pin count, and is suitable for chip package with high-frequency (i.e. radio frequency) transferring.
FIG. 1 is a side view of a conventional quad flat non-lead flip chip package. FIG. 2 is a bottom view of a conventional quad flat non-lead flip chip package of FIG. 1.
Please refer to FIGS. 1 and 2. The conventional quad flat non-lead flip chip package 100 comprises a chip 110, leads 120 and a molding compound material 130. The chip 110 has an active surface 112 and a corresponding backside surface 114. The active surface 112 refers to a surface having active elements. Further, bonding pads 116 are located on the active surface 112 of the chip 110. The bonding pads 116 are usually exposed through openings of a passivation layer (not shown).
Each of the leads 120 has an upper surface 122 and a lower surface 124. The bonding pads 116 of the chip 110 are respectively connected with the upper surface 122 of the leads 120 through bumps 140, such that the bonding pads 116 are electrically connected with the leads 120. The molding compound material 130 encapsulates the chip 110, bumps 140 and leads 120 and exposes the lower surface 124 of each of the leads 120, as shown in FIG. 2. In other words, after finishing the encapsulating of the molding compound material 130, the lower surface 124 of each of the leads 120 is exposed for connecting with other carriers or elements.
In the conventional manufacturing process of a quad flat non-lead package, a solder mask layer 150 is usually formed on the upper surface 122 of the leads 120. The solder mask layer 150 has openings 152 for exposing partial region of the upper surface 122 of the leads 120. The exposed region is used as a bump connection region for the bumps 140 and leads 120. It is noted that the openings 152 of the solder mask layer 150 is used to limit the extent of the bumps 140 when formed. Since the solder mask layer 150 has the non-stick property against solder, it limits the solder range within the openings 152 when the bumps 140 are welded on the upper surface 122 of the leads 120. Therefore, the solder mask layer is able to control the height of bump collapse. However, the conventional solder mask layer 150 needs a photo-masking process to define positions of openings 152, which increases the manufacturing difficulty and manufacturing cost. Besides, after the molding process, delamination between the molding compound material 130 and the solder mask layer 150 and between the solder mask layer 150 and leads 120 will reduce the reliability of package.